SINGH, Prerna, SINGH, Mansi, DUBEY, Pallavi, YADAV, Priyanshu, SURESH, Shaina und RAI, Amrita, 2025. A Review of Low-Power 32-Bit Multiplier Based on 18 nm Fin FET Technology. In: . 18 September 2025.
Elsevier - Harvard (with titles)Singh, P., Singh, M., Dubey, P., Yadav, P., Suresh, S., Rai, A., 2025. A Review of Low-Power 32-Bit Multiplier Based on 18 nm Fin FET Technology, in: . https://doi.org/10.1109/ICRITO66076.2025.11241364
American Psychological Association 7th editionSingh, P., Singh, M., Dubey, P., Yadav, P., Suresh, S., & Rai, A. (2025, September 18). A Review of Low-Power 32-Bit Multiplier Based on 18 nm Fin FET Technology. https://doi.org/10.1109/ICRITO66076.2025.11241364
Springer - Basic (author-date)Singh P, Singh M, Dubey P, Yadav P, Suresh S, Rai A (2025) A Review of Low-Power 32-Bit Multiplier Based on 18 nm Fin FET Technology
Juristische Zitierweise (Stüber) (Deutsch)Singh, Prerna/ Singh, Mansi/ Dubey, Pallavi/ Yadav, Priyanshu/ Suresh, Shaina/ Rai, Amrita, A Review of Low-Power 32-Bit Multiplier Based on 18 nm Fin FET Technology, 2025, .