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Result: Using Java optimized processor as an intellectual property core beside a RISC processor in FPGA

Title:

Using Java optimized processor as an intellectual property core beside a RISC processor in FPGA

Authors:

Source:

Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014) Design & Test Symposium (EWDTS), 2014 East-West. :1-6 Sep, 2014

Relation:

2014 East-West Design & Test Symposium (EWDTS)

Database:

IEEE Xplore Digital Library

*Result*: Using Java optimized processor as an intellectual property core beside a RISC processor in FPGA