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Treffer: MOSTAR: Multi-Stage Hierarchical Bayesian Optimization for Substructure-Aware High-Dimensional Analog Circuit Sizing

Title:
MOSTAR: Multi-Stage Hierarchical Bayesian Optimization for Substructure-Aware High-Dimensional Analog Circuit Sizing
Authors:
Fan, Weijian, Zhang, Haoyi, Lin, Weibin, Wang, Runsheng, Lin, Yibo
Source:
2026 31st Asia and South Pacific Design Automation Conference (ASP-DAC) Design Automation Conference (ASP-DAC), 2026 31st Asia and South Pacific. :653-659 Jan, 2026
Relation:
2026 31st Asia and South Pacific Design Automation Conference (ASP-DAC)
Database:
IEEE Xplore Digital Library