• Fortran High-Level Synthesis:...

*Result*: Fortran High-Level Synthesis: Reducing the Barriers to Accelerating HPC Codes on FPGAs

Title:
Fortran High-Level Synthesis: Reducing the Barriers to Accelerating HPC Codes on FPGAs
Authors:
Rodriguez-Canal, Gabriel, Brown, Nick, Dykes, Tim, Jones, Jess, Haus, Utz-Uwe
Source:
2023 33rd International Conference on Field-Programmable Logic and Applications (FPL) FPL Field-Programmable Logic and Applications (FPL), 2023 33rd International Conference on. :10-18 Sep, 2023
Relation:
2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)
Database:
IEEE Xplore Digital Library